1. Field of Invention
Embodiments of the present invention relate to a semiconductor device and an information processing system, and particularly relates to a semiconductor device comprised of a plurality of stacked semiconductor chips and an information processing system.
2. Description of the Related Art
Recently, in order to increase the memory capacity per a package, a stacked-type semiconductor device, which is formed by integrating a front-end part and a back-end part of a DRAM (Dynamic Random Access Memory) in separate chips, respectively, and stacking them, has been proposed (see Japanese Patent Application Laid-Open No. 2012-216652 (corresponding US Patent Application Publication No. 2012/0250387 A1) (Patent Literature 1), Japanese Patent Application Laid-Open No. 2013-206255 (corresponding US Patent Application Publication No. 2013/0258788 A1) (Patent Literature 2), and Japanese Patent Application Laid-Open No. 2011-81885 (corresponding US Patent Application Publication No. 2011/0087811 A1) (Patent Literature 3). Note that these literatures are incorporated by reference.
According to such a stacked-type semiconductor device, since the occupied area that can be allocated to a memory core is increased in the core chips in which the back-end part is integrated, the memory capacity per a single core chip can be increased. On the other hand, since the interface chip in which the front-end part is integrated can be fabricated in a process different from that of the memory core, circuits thereof can be formed by high-speed transistors. Moreover, a plurality of core chips can be allocated to the single interface chip; therefore, a semiconductor device that is extremely high-capacity and high-speed as a whole can be provided.
In a stacked-type semiconductor device of this type, operation timing is sometimes different in each core chip due to process variations, voltage variations, etc. Therefore, there has been a problem that the timing margin of data transfer is reduced in transfer of read data from the core chip to the interface chip or transfer of write data from the interface chip to the core chip.
In consideration of this point, in the semiconductor devices described in Patent Literatures 2 and 3, buffer circuits for adjusting the output timing of read data and the receiving timing of write data are provided on each of core chips, thereby eliminating the lag in the timing of each of the core chips.